Generally, a DRAM unit cell comprises a MOS transistor, a bit line and a storage capacitor. A storage electrode of the storage capacitor is electrically connected to a source electrode of the MOS transistor through a buried contact (BC) hole. The bit line is electrically connected to a drain electrode of the MOS transistor through a direct contact (DC) hole. In case of capacitor-over-bit line (COB) structure, the storage capacitor is formed over the bit line, and the BC hole is formed between the bit line of the cell and the bit line of an adjacent cell. There are two different representative methods in forming the COB structure, as described followings.
In first method, a BC hole is formed separately to the process for forming a capacitor-defining hollow, in which the storage electrode is to be formed. That is to say, a bit line is formed on a lower insulating film. A BC hole is formed by etching a portion of the lower insulating film. The BC hole may be preferably filled by a conductive BC plug. Subsequently, an upper insulating film is formed on the resultant structure. A capacitor-defining hollow is formed by etching a portion of the upper insulating film. A storage electrode is formed in the hollow and electrically connected to an underlying MOS transistor by way of the BC hole.
Meanwhile, in second method, a BC hole is formed continuously to the process for forming a capacitor-defining hollow. That is to say, a bit line is formed on a lower insulating film. An upper insulating film is formed on the bit line. A capacitor-defining hollow is formed by etching a portion of the upper insulating film. A BC hole is formed by etching a portion of the lower insulating film. The etching for forming the BC hole is performed continuously to the etching for forming the hollow.
The first method is more complex than the second one. Moreover, A resistance between the storage electrode and the transistor is unfavorably high in a DRAM unit cells made by the first method compared to the second method. Nevertheless, the first method is more widely adopted in commercial manufacturing field. This is because a misalignment problem, which is described in followings, is known to be more serious in the second method than in the first method.
In the continuing trend to higher memory capacity, it has been constantly needed to reduce the unit cell size of semiconductor devices. In order to decrease the cell size of a DRAM device having COB structure, it is essential to reduce a distance between the BC hole and the DC hole as well as a distance between the BC hole and the bit line. However, the reduced distances may weaken immunity to misalignment during the manufacturing process of the DRAM device, especially in a design rule of 0.2 um or less. The misalignment problem may induce an electrical short (an unfavorable electrical connection) between the storage capacitor and the bit line. The misalignment problem will be described in detail hereinafter with reference to the accompanying drawings.
FIGS. 8a through 8c are for illustrating one example of conventional DRAM devices, which is formed by the second method. FIG. 8a is a schematic plan view illustrating a portion of a unit cell array. FIGS. 8b and 8c are cross-sectional views of FIG. 8a taken along a line 8B-8B′ and a line 8C-8C′ respectively.
Referring to FIG. 8a through 8c, an isolation region 114 is formed on a semiconductor substrate 110, thereby defining active regions 112 in the substrate 110. The isolation region 114 may be formed by using either LOCOS (Local Oxidation of Silicon) technique or trench technique. For better understanding of the plan view, the active regions 112 and the isolation region 114 are not shown in FIG. 8a. On the resultant structure, a plurality of gate patterns is formed to extend in a first direction. Each of the gate patterns comprises a conductive gate electrode 118, a gate dielectric layer 116, an insulating gate capping layer 120 and insulating gate spacers 122. The gate electrode 118 is formed on the substrate 110. The gate dielectric layer 116 is formed between the gate electrode 118 and the substrate 110. The gate capping layer 120 is formed on the gate electrode 118. The gate spacers 122 are formed on the sidewalls of the gate electrode 118. For better understanding of the plan view, the gate dielectric layer 116, the insulating gate capping layer 120 and the gate spacers 122 are not shown in FIG. 8a. The gate patterns are spaced apart to each other with a constant distance, thereby defining a plurality of spatial lanes therebetween.
An insulating pad-defining layer 125 is formed on the gate patterns and the substrate 110. The pad-defining layer 125 is patterned by photo/etch technique to form a plurality of pad holes, which expose a portion of the active regions 112. Though not shown in the drawings, a conductive pad layer is formed on the pad-defining layer 125 and the exposed portion of the active regions 112. An upper portion of the pad layer and an upper portion of the pad-defining layer 125 are polished out by CMP (Chemical Mechanical Polishing) technique to expose the gate capping layers 120. As a result, either the rows of BC pads 124a or the rows of DC pads 124b are formed on each of the plurality of spatial lanes as shown in the drawings. The rows of the BC pads 124a are formed on every second spatial lane, and the rows of the DC pads 124b are also formed on every second spatial lane. That is to say, the rows of the BC pads 124a and the rows of the DC pads 124b are formed alternatively and one by one on the spatial lanes.
As shown in FIG. 8a, the BC pads 124a are arranged in periodicity in the first direction with a first cyclical distance. Similarly, the DC pads 124b are arranged in periodicity in the first direction with a second cyclical distance. The second cyclical distance is twice the first one. As shown in FIG. 8b, each of the active regions 112 has two of the BC pads 124a and one of the DC pads 124b. The BC pads 124a are located on two ends of the active regions 112. The DC pads 124b are located on the centers of the active regions 112.
A lower insulating film 126 is formed on the BC pads 124a, the DC pads 124b and the gate patterns. The lower insulating film 126 is patterned by photo/etch technique to form a plurality of DC holes, which expose the DC pads 124b. The DC holes are filled with conductive DC plugs 129a. 
A plurality of bit line patterns is formed on the lower insulating film 126. Each of the bit line patterns comprises a conductive bit line 129, an insulating bit line capping layer and bit line spacers. The bit line 129 is formed on the lower insulating film. The bit line capping layer is formed on the bit line 129. The bit line spacers are formed on sidewalls of the bit line 129. For better understanding of the drawings, the bit line capping layers and bit line spacers are not shown in the drawings. The bit lines 129 are electrically connected to the corresponding ones of the DC plugs 129a. The plurality of the bit line patterns is extended in a second direction. The second direction is perpendicular to the first direction.
An intermediate insulating film 135 and an upper insulating film 139 are formed on the resultant structure. The upper insulating film 139, the intermediate insulating film 135 and the lower insulating film 126 are patterned sequentially and continuously by photo/etch technique. As a result, a plurality of hollows 141 is formed through the upper insulating film 139, the intermediate insulating film 135 and the lower insulating film 126. Each of the hollows 141 includes an upper hollow and a lower hollow. The upper hollow (i.e., capacitor-defining hollow) is a portion of the hollow that is surrounded by the upper insulating film 139. The lower hollow (i.e., BC hole) is a portion of the hollow that is surrounded by the intermediate insulating film 135 and the lower insulating film 126. The BC holes expose corresponding ones of the BC pads 124a. 
Subsequently, storage electrode 143 is formed in each of the hollows by well-known method. The storage electrodes 143 are preferably formed of polysilicon. The storage electrodes 143 are connected to corresponding ones of the BC pads 124a through the BC holes. Though not shown, a capacitor dielectric layer and a plate electrode are formed on the storage electrodes 143.
As described above, the hollows are formed by photo/etch technique. Therefore, the alignment of the photo/etch technique determines distance between the storage electrodes 143 and the DC plugs 129a (denoted by W2) as well as distance between the storage electrodes 143 and the bit lines 129. The distances should be decreased to obtain a high packing density of the devices. However, the deceased distances result in weak immunity to misalignment during the manufacturing process. That is to say, it is very critical to maintain accurate alignment during the process for forming the hollows to prevent the electrical short between the storage capacitor and the bit line. Accordingly, the need for method for forming DRAM devices of COB structure having an increased immunity to misalignment during the manufacturing process remains.